In recent years the integration degree of semiconductor memories has been continually increasing. However, in conventional memory cells used in a semiconductor memory, resistors are used as load impedances of flip-flop transistors which are used in the memory cells, and also, an isolation between transistors is required, so that the conventional memory cells are large in size. Therefore, a memory chip is also large in size and the density of the memory chips which are included in one wafer can not be increased, so that the cost of a semiconductor memory is expensive.
For the purpose of obtaining memory cells having small dimensions, memory cells using Integrated Injection Logic (I.sup.2 L) are used.
Such I.sup.2 L memory cells can be formed with high integration density as disclosed, for example, in the articles "Write Current Control and Self Powering in a Low Power Memory Cell", IEEE, SSC, Jun., 1973, and "Superintegrated Memory Shares Functions on Diffused Islands", Electronics, Feb. 14, 1972, p83-p86. The former discloses a method of controlling a write current to the I.sup.2 L memory cell and the latter discloses a basic idea with respect to the I.sup.2 L memory cell.
As disclosed in the above mentioned articles, the I.sup.2 L memory cell comprises: a pair of first and second transistors, which have emitters forming an injector which is connected to a work line W+, and said first and second transistors have a first polarity; a pair of third and fourth transistors, which have a collector connected to a collector of the first or second transistor, a base of the third transistor which is connected to the collector of said fourth transistor and a base of the fourth transistor which is connected to the collector of said third transistor, and which have a second polarity, and; a bulk, that is, a word line W-, which is connected to the bases of the first and second transistors and to emitters of the third and fourth transistors.
The I.sup.2 L memory cells are arranged as the memory array. In these I.sup.2 L memory cells, the word line W- is formed as the bulk, and the bulk usually consists of two n-type layers, an epitaxial layer and a buried layer. The epitaxial layer is formed on the buried layer which has higher density of the impurity than the epitaxial layer. Therefore, the bulk, that is, the word line W-, has a larger resistance than a metalic wire, and this resistance exists between each cell.
When the bulk is used as the word line W- which supplies the hold current, the characteristics of the cells are different in accordance with the positions of the cells in the line of the array. In other words, in the conventional I.sup.2 L memory the hold current source is provided at only one end of the word line W-. Therefore, injection currents which are supplied to the memory cells connected to the word line are not uniform due to the bulk resistance. Consequently, in the memory cell arranged near the end of the word line, a write threshold current Iwth increases and, also, the width of the write pulse increases.
In order to equalize the injection currents supplied to I.sup.2 L memory cells, the inventors of the present invention invented, prior to the present invention, an improved I.sup.2 L memory in which a hold-current source is provided at each end of the word line W-, as disclosed in the U.S. Patent Application Ser. No. 48256, filed on June 13, 1979, now U.S. Pat. No. 4,231,108. By this improved I.sup.2 L memory, almost uniform distribution of the injection currents was obtained. However, there are still problems in this prior I.sup.2 L memory. That is, because two current sources are required in each memory-cell array in a word line, the integration degree is lowered. In addition, because two wiring lines are required for connecting bases and emitters of the two current sources at the ends of a word line, the wiring becomes complex.